Inside the Motorola 6820/1 PIA
(Peripheral Interface Adaptor)
Originally published on September 18th, 1999 in the Usenet newsgroup: Rec.Games.Pinball
The 6820/1 PIA can be classed as two seperate 8-bit ports with interrupt generating pins in one device. A two "channel" device if you like.
Each channel has an 8-bit (byte wide) port and any of those 8 port pins can be configured as an input or output in any configuration. The ports are refered to as "port A" and "port B". The interrupt generating pins are CA1 and CA2 for port A and CB1, CB2 for port B. These are inputs on the the other side of the PIA (to the "outside world" - not the processor bus side). Cx1 is *always* an interrupt input pin, Cx2 can be either an interrupt generating pin or a basic output pin as per the ports.
Any state change received on the Cxx pins
appear on the IRQ (Interrupt ReQuest) pins on the bus side of the PIA
(providing Cx2 is set to generate interrupts). These pins - IRQa/b are
tied together and also
The PIA also has three Chip Select pins
(CSx) which bring the PIA out of standby or "tri-state" operation via
address decoding. In it's tri-state, the data bus lines are
high impedance - virtually open circuit so
There are also two Register Select pins
(RS0/1) and these two bits determine which of the internal six registers
are being read from or written too. However, you don't need to be a rocket
scientist to work
Register Select Bits
1 0 (Register select bits 1-0)
0 0 Peripheral Register A: Actual port data bits/pins
Port B has exactly the same configuration but substisute "B" for "A" and "2" for "1" on the CA/B inputs...
Out of reset. The PIA will always configure itself to both ports being inputs and all interrupts disabled. The processor has to reconfigure this for proper in-game operation.
So if you were to set up port A using
6800/2/8 assembly, it would look like this (for example):
A_direct equ $2000
;set port B...
The set-up and programming of the PIA
depends on it's function. For instance, port "A" may set set to all outputs
and each bit individually set high in sequence to sweep the switch
matrix. Port "B"" may be
Cx2 is the only pin that can be configured as I/O. Cx1 is interrupt generating only.
bit1 bit0 Cx1 state IRQa/b status
0 0 High>Low
Disabled (High) =1 on low transition Cx1 pin
Cx2 as Interrupt Generating
bit5 bit4 bit3 Cx2 state IRQa/b
status bit6 state
0 0 0 High>Low
Disabled (High) =1 on low transition Cx2
Cx2 as I/O
bit5 bit4 bit3 bit2 Function
0 0 0 Cx2 low after
CPU reads port A data next low clock