Williams System (Level 6) Memory Protect Circuit Description

(Originally published April 20th, 1996 on the Usenet newsgroup Rec.Games.Pinball)

It's time for me to ramble on about the technical side of pinball - tonight's episode is the memory protect circuit from the Williams System 6 MPU board.

The much talked about, extremely difficult to get in the UK, 4-bit x 128 CMOS static RAM commonly known as the 5101P RAM IC is used to store book keeping functions on the early Williams solid state games. The audit functions 00-12 (stored in the 5101) are write protected whenever the coin-op door is open. The circuit looks thus;

(Appalling but obligatory ASCII drawing coming up -- and don't worry, most 5101's do usually have more than 1 pin).

* - denotes signal is active low

 |         |
 |         |
 |  5101   |            IC27 (also battery backed)
 |  RAM    |
 |         |              ____ 1
 |         |20         3 |4071|-----< R/W* (from 6802/8 uP)
 |     R/W*|-------------|*OR*|2
 |_________|             |____|-----.
                       10 ____      |
              A7 >-------|7408|8    |   R37
                       9 |AND |-----O--[300k]---< CMOS +V (BAT)
        TP3 O-----O------|____|
                  |               IC12
                  |  J5
  +5v             '-O--O-.
   |   R14     9 ____    |
   O--[4K7]--O--|7400|8  |
             |10|NAND|O--' IC24
             |  memory protect*            ____
             '-----------------<1J3/1<----O    O-------> To Earth

The circuit might look a bit daunting to beginners, but, it's really quite simple:

IC24 is wired as an inverter. When the coin door is open both inputs are held high via the 4.7k resistor at R14, this in turn forces the output low. Don't worry about jumper J5 and test point TP3 - their inclusion here is only to keep in line with the original schematic.

The output of this NAND gate is fed into the AND gate at IC 12 pin 9, this gate requires both inputs to be high to switch it's output on, but as the NAND gate always outputs a low signal with the coin door open it never will.

Following on from this scenario: If an address is placed on the bus that corresponds to the 5101 (100h - 17Fh), regardless of whether the 6802/8 uP asserted a read or write cycle (and adjusted the R/W* signal accordingly) the 5101 will always be held in "read" mode because the input at pin 2 of IC27 is held high via the battery through R37 (OR gates only go low when *both* inputs are low, all other input combinations will force the output high).

Now then, if the coin door is closed the circuit acts differently. With the coin door shut, the memory interlock switch "grounds" (connects them to earth) the inputs of the NAND gate at IC24. The gates output now switches to high. In turn this is fed to the AND gate input at pin 9 of  IC12 as previously discussed, so, everytime address line A7 goes high during an access to the 5101, the AND gate switches it's output on.

The output of the AND gate can actually *sink* current too because of transistors in the output stages and thats exactly what happens next: The output transistors turn on in the 7408 and pull the line between R37 and pin 2 of the OR gate IC27 down (low). This means that as the "write"  
signal is active low from the 6802/8 uP and the other input is low too (pin 2), the OR gate output will be low also, translating to a "write" request on pin 20 of the 5101.

Not so difficult after all, eh? You'll also notice (if you have schematics) that IC27 is active even with the power off because power is supplied to it via the battery (the 4071 is a CMOS device), also pin 2 is held high during standby translating to the 5101 being held constantly in "read" mode.

The reason? - it's not unusual for power supplies to duck to dangerously low digital levels causing undetermined high's and low's - this can be dangerous during write cycles as the data being written can change state, which, translates to garbage being written into the memory location. The  
battery will remain at a constant voltage during these fluctuations and force the 5101 into a "read" mode to prevent this from happening via pin 2 of IC27 as above. Power downs and power up's (power cycling) can be classed as "fluctuations" too.

Thruth Tables

Here are the truth tables for the gates listed above for your reference;

           AND                    NAND                      OR

IN1 | IN2 | OUT |       IN1 | IN2 | OUT |       IN1 | IN2 | OUT |
----|-----|-----|       ----|-----|-----|       ----|-----|-----|
low | low | low |       low | low |high |       low | low | low |
high| low | low |       high| low |high |       high| low |high |
low |high | low |       low |high |high |       low |high |high |
high|high |high |       high|high | low |       high|high |high |
----------------        ----------------        ----------------